1. Field of the Invention
The present invention relates to a skew adjusting method in an IC testing apparatus for testing various kinds of semiconductor integrated circuits (each referred to as IC, hereinafter) and determining whether they are defectless (pass) or defective (failure), and more particularly, to an adjusting method for conforming the timing at which a test pattern signal is applied to each of terminals of an IC under test and the timing at which a response output signal outputted from the IC under test is fetched or read out, to a predetermined set value for each terminal, called skew adjusting method in this field (hereinafter referred to skew adjusting method), and a pseudo device which is used in this skew adjusting method.
2. Description of the Related Art
In an IC testing apparatus for testing ICs such as, for example, memories, it is conventional that an adjustment in which the timing for applying a test pattern signal to each of input terminals (a data input terminal and an address input terminal) of an IC under test and the timing for reading out a response output signal from an output terminal of the IC under test or an 110 terminal of the IC under test in its output mode are conformed to a predetermined set value for each terminal, is periodically conducted. This adjustment is commonly called skew adjustment In this technical field.
In a test head of the IC testing apparatus, there is housed a printed board, called a pin card in this field, which contains, for example, a driver for applying a test pattern signal to an IC under test through an IC socket mounted on top of the test head, and a comparator for comparing a response output signal fetched through the IC socket from the IC under test with an expected value signal, and the like. The printed board will hereinafter be referred to as pin card. Usually there are housed a plurality of pin cards the number of which corresponds to the number of terminals (pins) of an IC under test. FIG. 3 schematically depicts, by way of example, the circuit configuration of such a pin card. Since pin cards 11A, 11B, 11C, . . . , 11N have the same circuit configuration with one another, there is shown in FIG. 3 the circuit configuration of only the pin card 11A. The pin cards 11A through 11N are each designed so that when they are placed in the test head at predetermined positions thereof, the output terminals of the drivers are electrically connected to an IC socket and one input terminal of each of the comparators is electrically connected to the IC socket.
As depicted in FIG. 3, the pin card 11A comprises a waveform generator FF, a driver DR for amplifying a test pattern signal generated by the waveform generator FF and applying the amplified test pattern signal to an IC under test via a terminal P.sub.1 of an IC socket 10, and a voltage comparator CP for comparing a response output signal from the IC under test with an expected value signal.
The IC socket 10, to which the IC under test (not shown) is to be electrically connected, has terminals (pins) P.sub.1, P.sub.2, P.sub.3, . . . , P.sub.N corresponding in number to terminals (pins) of the IC under test to which the terminals P.sub.1 to P.sub.N are connected. To the terminates P.sub.1 to P.sub.N are each connected the output terminal of the driver DR and one input terminal of the voltage comparator CP of the corresponding one of the pin cards 11A to 11N.
The waveform generator FF is formed, in this example, by an S-R flip-flop provided with a set terminal S and a reset terminal R. When supplied at its set terminal S with a set input signal PSET (shown in FIG. 4B) from an input terminal SET of the pin card 11A via a variable delay circuit DRY1, the S-R flipflop FF generates a driving signal V.sub.DR that goes to a logical H (high level) as depicted in FIG. 4D.
On the other hand, when supplied at its reset terminal R with a reset input signal P.sub.RESET (shown in FIG. 4C) from an input terminal RESET of the pin card 11A via a variable delay circuit DRY2, the S-R flip-flop FF makes the driving signal VDR L-logic (lowlevel) as depicted in FIG. 4D.
In this way, the S-R flip-flop FF generates the driving signal V.sub.DR in response to the application thereto of the set input signal P.sub.SET and the reset input signal P.sub.RESET. The driving signal VDR is amplified by the driver DR, from which it is fed as a test pattern signal via the corresponding terminal P1 of the IC socket 10 to the corresponding input terminal (an address input terminal and a dedicated input terminal, or an Input terminal of a combination I/O terminal in the input mode) of the IC under test. Needless to say, the waveform generator FF is not limited specifically to the S-R flipflop but may also be formed by other devices or circuits as long as they serve the intended purpose.
The set input signal P.sub.SET and the reset input signal P.sub.RESET are delayed for .tau..sub.1 and .tau..sub.2, respectively, relative to the generation timing of period pulses P.sub.RET that define the test period T.sub.TES as shown in FIG. 4A, and then they are input into the set input terminal SET and the reset input terminal RESET of each of the pin cards 11A to 11N. The delay times r and .tau..sub.2 are determined by the condition for the generation of the test pattern.
Now, assuming that the delay times of the set and reset input signals PSET and PRESET fed to the input terminals SET and RESET of all the pin cards 11A to 11N are .tau..sub.1 and .tau..sub.2 depicted in FIGS. 4B and 4C, respectively, test pattern signals ought to be applied in the same phase (at the same timing) to the respective terminals P.sub.1 to P.sub.N of the IC socket 10.
In practice, however, due to variations in the line lengths between the pin cards 11A to 11N and the corresponding terminals P.sub.1 to P.sub.N of the IC socket 10, or by some other cause, the signal propagation delay time T.sub.pd shown in FIG. 3 varies accordingly, resulting in variations In the timing of arrival of the driving signals VDR at the terminals P1 to PN of the IC socket 10. To accommodate the variations in this timing and hence ensure in-phase application of the test pattern signals to the IC socket, the pin cards 11A to 11N are each provided with the aforementioned variable delay circuits DRY1 and DRY2. By controlling the delay times of the variable delay circuits DRY1 and DRY2, the phases of the driving signals V.sub.DR to be supplied to all the terminals P.sub.1 to P.sub.N of the IC socket 10 are adjusted into coincidence with the phases of the set and reset input signals P.sub.SET and P.sub.RESET fed to the input terminals SET and REST of the pin cards 11A to 11N. This is the aforementioned skew adjustment.
In addition, when there are variations in the propagation delay time T.sub.pd between the pin cards 11A to 11N and the corresponding terminals of the IC socket 10, variations also result in the propagation time for the response output signal read out of the IC under test to reach the voltage comparator CP of the corresponding one of the pin cards 11A to 11N. To accommodate the variations, there is placed l variable delay circuit DRY3 in a path over which a strobe pulse P.sub.STRB is supplied to the voltage comparator CP via a strobe input terminal STRB of each pin card, by which skew adjustments are made on the voltage comparator CP side as well.
Next, a description will be given of conventional skew adjusting methods on the driver DR side and on the voltage comparator CP side.
Conventionally, to make skew adjustments on the driver DR side, a standard voltage comparator STDCP is provided as standard phase detecting means as shown in FIG. 3; output terminals of the pin cards 11A to 11N are selectively connected via a relay matrix RMAX to the standard voltage comparator STDCP in a sequential order to make the skew adjustment for each of the pin cards 11A to 11N. The skew adjustment for the pin card 11A will be described below by way of example.
The standard voltage comparator STDCP is provided with first and second comparators CP.sub.1 and CP.sub.2 as depicted in FIG. 5. The comparators CP.sub.1 and CP.sub.2 form a window comparator. In the standard voltage comparator STDCP the first comparator CP.sub.1 outputs L or H logic, depending on whether an input signal V.sub.X is larger or smaller than a comparison (reference) voltage V.sub.H. On the other hand, the second comparator CP.sub.2 outputs L or H logic, depending on whether the input signal V.sub.X is smaller or larger than a comparison voltage V.sub.L. Accordingly, by monitoring the logical values provided at output terminals TVH and TVL of the standard voltage comparator STDCP, it is possible to detect what relationships the input signal V.sub.X bears to the comparison voltages V.sub.H and V.sub.L.
Assume that the voltage relationships between the comparison voltages V.sub.L and V.sub.H and the input signal V.sub.X are set, for example, such that voltages a little higher than the L-logic level and a little lower than the H-logic level of the input signal V.sub.X are the comparison voltages V.sub.L and V.sub.H, respectively, as shown in FIG. 6B. Further, let it be assumed that the phase of a reference clock CLK, which is applied as a strobe pulse to each of the comparators CP.sub.1 and CP.sub.2, is shifted for each test period T.sub.TES (FIG. 6A) in a sequential order of CLK.sub.1, CLK.sub.2, . . . , CLK.sub.N as depicted in FIG. 6C, thereby shifting the timing of comparison by the comparators CP.sub.1 and CP.sub.2
In this instance, when the voltage of the input signal V.sub.X is lower than the comparison voltage V.sub.L, L logic and H logic are provided at the output terminals TVL and TVH, respectively. When the voltage of the input signal V.sub.X is intermediate between the comparison voltages V.sub.H and V.sub.L, H logic is provided at both of the output terminals TVL and TVH. When the voltage of the input signal V.sub.X is higher than the comparison voltage V.sub.H, H logic and L logic are provided at the output terminals TVL and TVH, respectively. Thus, the state of the input signal VX can be known by monitoring the logical values that are provided at the output terminals TVL and TVH of the standard voltage comparator STDCP. The skew adjustment on the driver DR side is an adjustment that detects, for example, the timing of the rise edge of the input signal V.sub.X through utilization of such characteristics of the voltage comparators, then measures the delay time of the input signal V.sub.X based on the detected timing of its rise edge, and sets the delay times of the variable delay circuits DRY1 and DRY2 so that the delay time of the input signal V.sub.X becomes as predetermined.
More specifically, according to the conventional method for making the skew adjustment on the driver DR side, the delay times of the variable delay circuits DRY1 and DRY2 are preset at reference values (for example, at central values of the variable delay time widths), then the set and reset input signals P.sub.SET and P.sub.RESET set to be delayed by predetermined time intervals, for example, by the time intervals .tau..sub.1 and .tau..sub.2 shown in FIG. 4, are input into the delay circuits, and the driving signal V.sub.DR is provided from the driver DR.
On the other hand, the IC socket 10 is held disconnected from the IC under test, and is caused to reflect a signal at the terminal P.sub.1. As a result, the standard voltage comparator STDCP is supplied with a direct wave R.sub.X1 output from the driver DR and a reflected wave R.sub.X2 delayed by a time interval T.sub.Q twice longer than the propagation delay time T.sub.pd between the pin card 11A and the terminal P.sub.1 of the IC socket 10 as depicted in FIG. 7C.
Hence, the comparison voltages V.sub.H and V.sub.L of the standard voltage comparator STDCP are set at levels that cross a timing point T.sub.1 in the rise edge of the direct wave R.sub.X1 and a timing point T.sub.2 in the fall edge of the reflected wave R.sub.X2 as depicted in FIG. 7C. And the phase of the reference clock CLK, which is applied as the strobe pulse P.sub.STRB to the standard voltage comparator STDCP, is slightly shifted for each test period T.sub.TES in a sequential order of P.sub.STRB1, P.sub.STRB2, . . . , P.sub.STRBn as depicted in FIG. 7D. By this, It is possible to detect the timing T.sub.1 and T.sub.2 of arrival of the direct wave R.sub.X1 and the reflected wave R.sub.X2 at the standard voltage comparator STDCP. Based on the thus detected timing T.sub.1 and T.sub.2, the time difference T.sub.Q between the direct wave R.sub.X1 and the reflected wave R.sub.X2 can be detected. By dividing the time difference T.sub.Q by 2, it is possible to determine the propagation delay time T.sub.pd between the pin card 11A and the terminal P.sub.1 of the IC socket 10.
The above measurement is carried out for each pin card to determine the propagation delay time T.sub.pd. Then, for example, the central value in the range of variations in the propagation delay time T.sub.pd is set as a reference value, and the deviation of the actually measured propagation delay time T.sub.pd from the reference value is computed for each pin card. And a delay time corresponding to the computed deviation is set in each of the variable delay circuits DRY1 and DRY2 of the respective pin cards 11A to 11N, with which the skew adjustment on the driver side is completed.
This is followed by adjusting the comparison timing of the voltage comparators CP mounted on the pin cards 11A to 11N. The voltage comparator CP of each pin card may be identical in construction with the standard voltage comparator STDCP depicted in FIG. 5. By setting the comparison voltage V.sub.L at a voltage slightly above the L-logic level, it is possible to detect the timing of the rise edge of the driving signal V.sub.DR that the driver DR outputs.
In concrete terms, the adjustment of the timing of comparison by the voltage comparator CP is made by: inputting the driving signal V.sub.DR, shown In FIG. 9B, directly into the voltage comparator CP from the driver DR; detecting timing T.sub.S at which the rise edge of the driving signal V.sub.DR crosses the comparison voltage V.sub.L depicted in FIG. 9B; and setting the detected timing T.sub.S in the variable delay circuit DRY3 provided in the supply path of the strobe pulse P.sub.STRB from the strobe input terminal STRB to the voltage comparator CP on each pin card as shown in FIG. 8. That is, the variable delay circuit DRY3 is set in what is called a through state, then the timing T.sub.S of arrival thereto of the driving signal V.sub.DR from the driver DR is measured, and the delay time of the variable delay circuit DRY3 is set such that the measured timing T.sub.S coincides with the delay time .tau..sub.1 of the set signal P.sub.SET By this, the detected timing of the voltage comparator CP can be made to coincide with the delay time on the driver DR side. In FIG. 8 the parts and elements corresponding to those in FIG. 3 are identified by the same reference characters.
As described above, the traditional skew adjusting method utilizes the reflected wave particularly for the skew adjustment on the driver side, and in addition, provides the reflected wave via the relay matrix RMAX to the standard voltage comparator STDCP to measure the delay of phase or delay of the reflected wave between the driver DR and each of the terminals P.sub.1 to P.sub.N of the IC socket 10; hence, the conventional method has a defect that no accurate delay of phase can be measured.
In other words, the relay matrix RMAX is used only to connect the standard voltage comparator STDCP to the pin cards 11A to 11N during the skew adjustment, and is not used for IC test. Besides, it is switched to connect the standard voltage comparator STDCP to the drivers DR of the respective pin cards one after another; hence, if the delay time by the relay matrix RMAX varies with Its switching, then an error is caused in the propagation delay time between the driver DR and each pin P of the IC socket which is measured for each pin card 11. Since there is no real chance that there is no difference in the line lengths between the relay matrix RMAX and the respective pin cards, the delay time by the relay matrix RMAX varies with its switching. Therefore, it is difficult to implement accurately-in-phase application of test pattern signals from all the pin cards 11A to 11N to the corresponding terminals P.sub.1 to P.sub.N of the IC socket 10.
Because of inaccurate skew adjustment on the driver side as mentioned above, the skew adjustment for the voltage comparator CP based on it also lacks accuracy.